Advances in the technology surrounding today's integrated circuits designs, such as microprocessors, continue at an astounding rate. As a result of these advances, integrated circuits are more dense and faster than ever. Moreover, integrated circuits have input/output (I/O) which are operating at higher frequencies than ever. In addition, integrated circuits are consuming more power than their predecessors. These factors are bringing about new challenges for packaging engineers.
On the issue of power consumption, today's microprocessors often consume up to 120 watts of power or more. With these microprocessors operating at a 1.2 volt level, 120 watts of power consumption means delivering significant amount of current, up to 100 amps, to these devices. A consequence of this is a requirement to dissipate a great amount of heat. As design advances continue, designs are predicted to approach 200 watts of power consumption in the near future. Successfully delivery of such power to today's and future integrated circuits has become, and will continue to be, a significant challenge.
The factors causing the increase in power consumption are numerous. One such factor is the operating speed of today's designs. Today, core speeds of microprocessors have surpassed 2 GHz. Similarly, bus speeds have increased as well; today's bus speeds have surpassed 400 MHz. As operating frequency increases for a given size integrated circuit, power consumption is also increased. This increase is due to, among other things, parasitic resistance of the motherboard, socket pins and electronic packaging. Unfortunately, the cost to reduce parasitic resistance on motherboards, socket pins and electronic packaging can be extensive. Thus, delivering increased power to today's designs without incurring a significant increase in cost is one challenge facing packaging engineers.
An additional issue facing today's packaging engineers with respect to integrated circuits is coupling associated with higher I/O signal switching speeds and the higher power being delivered to the integrated circuits. In addition to having more power and I/O signals to be delivered/facilitated than previous generations of designs, the desire is to have even smaller packaging of these integrated circuit designs. This is pushing the pins containing the higher speed I/O signals and pins providing increased power delivery closer together in the packaging. This, in turn, is creating further issues between the power delivered to an integrated circuit and the I/O signals entering and leaving the integrated circuit.
Thus, significant challenges face today's packaging engineers with respect to signal I/O and power delivery to today's integrated circuits.